Architecture Design and Evaluation of Ldpc Decoder on Tta Based Codesign Environment

High quality digital video transmission requires efficient and reliable data communication over broadcasting channels as there is a risk of data corruption associated during transmission. The near channel performance of Low Density Parity Check Codes (LDPC) has motivated its use in second generation Digital Video Broadcasting (DVB) standards for mobile, cable, satellite and terrestrial channels as an error correction code. But iterative decoding of LDPC codes provides significant implementation challenges as the complexity grows with the code size. This problem can be mitigated by exploiting the modular nature of the iterative decoding scheme for efficient parallel implementation. Transport Triggered Architecture (TTA) provides a processor template that exploits operation style parallelism and parallelism at data transport level. TTA-Based Codesign Environment (TCE) provides the necessary toolset to design a TTA processor. In addition, the toolset also provides the means to design application specific processors to accelerate the execution of the application and implement the processor on reconfigurable logic platform such as Field Programmable Gate Arrays (FPGAs) with ease. This work leverages TCE toolset to implement iterative decoding scheme such as reduced minimum sum algorithm on field programmable gate arrays. It also presents the throughput gains and evaluates the capabilities of the TTA architecture and the TCE toolset for the design of application specific instruction set processors.